The core grain has attracted much attention in the automotive market, and the continuous development of electrification and fierce competition forced the company to accelerate the design and production plans.
Electrification has ignited some of the enthusiasm of automobile manufacturers. Facing very short market windows and changing needs, these manufacturers are trying to maintain competitiveness.Different from the past, car manufacturers usually use the design cycle of five to seven years, and today's automotive technology is likely to be outdated within a few years.If they can't keep up, there will be a number of new startups to produce cheap cars, and these cars can quickly update or change their functions like software updates.
However, software has limitations in terms of speed, security and reliability, and customized hardware is the direction where many auto manufacturers are working hard now.This is the place of martial arts for core grains. The focus is now how to establish sufficient interoperability in the large ecosystem to make it a market that is plugged and played.The key factors for realizing the interoperability of car cores include standardization, interconnection technology, communication protocols, power supply and thermal management, security, testing and ecosystem collaboration.
Similar to board -level non -car applications, many design work is concentrated in the method of chip to chip, which has promoted many novel design considerations and weighing.At the chip level, due to the improvement of design performance requirements, various processors, chips,MemoryThe connection between I/O has become more and more complicated, which has triggered a series of standard activities.People have proposed different interconnection and interface types to meet different purposes, and emerging core -core techniques for special functions (processors, memory, I/O, etc.) are changing the chip design method.
Automotive original equipment manufacturers recognize that to control their destiny, they must control their SOC, David Fritz, vice president of Siemens EDA virtual and hybrid system.However, they don't understand how far EDA has gone since I went to college in 1982.In addition, they think they need to enter the process node, one of which coverModuleIt will cost $ 100 million.They can't afford it.They can't get talents because the talent pool is quite small.All these are added together, and the original equipment manufacturer realizes that to control their own destiny, they need a technology developed by others, but they can be combined as needed to have unique differentiated products.People are a future -oriented model year.Then it becomes financially feasible.What meets the requirements is core grains.
Core kernels can be optimized for specific functions, which can help car manufacturers use technical technologies that have been verified in various vehicle design to meet reliability, safety and security requirements.In addition, they can shorten the time of listing and eventually reduce the costs of different characteristics and functions.
In the past ten years, the demand for chips has been increasing.According to ALLIED Market Research, global car chip demand will increase from US $ 49.8 billion in 2021 to US $ 121.3 billion in 2031.This growth will attract more car chip innovation and investment, and core grains are expected to become a major beneficiary.
However, the maturity of the core grain market will take a while, and it may be launched in stages.At the beginning, suppliers will provide different styles of proprietary molds.The partners will then work together to provide core grains to support each other, as some suppliers have happened.Phase will be a commonly operated core, supported by UCIE or other interconnected solutions.
　Momentum is increasing
From a positive point of view, not all of this starts from scratch.In the board level, modules and subsystems always use board chip to chip interface, and will continue to do so.Various chips and IP providers (including Cadence, DIODE, Microchip, NXP, Renesas, Rambus, Infineon, ARM, and SynopSys) provide ready -made interface chips or IP to create interface chips.
The GM Chice Interconnect Express (UCIE) Alliance is the driving force behind the chip to the chip open interconnection standard.The organization's UCIE 1.1 specification released in August 2023.The members of the board include Alibaba, AMD, ARM, ASE, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung, etc.Industry partners show extensive support.AIB and Bunch of Wires (BOW) have also been proposed.In addition, ARM has just released its own Chiclet system architecture and updated AMBA specifications to standardize the Chiclet protocol.
Arif Khan, the director of the Cadence Design IP product marketing team, said: Driven by the necessity, Chiclet has appeared.The growing processor and SOC size are reaching the limits and scale of the standard line.The incremental income brought by the progress of process technology is lower than each onetransistorAnd the increase in design costs.The advancement of packaging technology (2.5D/3D) and chip inductors (such as UCIE) will promote the development of core grains.
Almost all cores used today are developed by large chip manufacturers such as Intel, AMD and Marvell because they can strictly control the characteristics and behaviors of these core grains.But all levels are working on work to open this market to more participants.When this happens, smaller companies can begin to use the achievements that have attracted much attention so far, and innovate around these development.
Guillaume Boillet, Guillaume Boillet, said: Many of us believe that the dream of having a ready -made, interactive core -grain combination may take several years to become a reality.He added that interoperability will come from the partner group, and they are solving the risk of incomplete norms.
This also enhances the attractiveness of FPGA and EFPGA, which can provide a certain degree of customization and update for on -site hardware.Chiclet is real, Geoff Tate, executive officer of Flex Logix.At present, a company that makes two or more core -grains is more economical than a company that has almost no good rate chip that has almost no good rate.Chiclet standardization seems to be far away.Even Ucie does not have a fixed standard.Not everyone agrees with UCIE, nude testing, and who is responsible for the problem when the integrated packaging cannot work.We do have some customers who use or are evaluating the EFPGA interface. The standards of these interfaces are constantly changing, such as Ucie.They can now implement chips and use EFPGA to adapt to future standard changes.
There are other efforts to support core grains, although for some different reasons -especially the increase in the cost of device expansion and the need to integrate more functions into the chip, and the chip's node is limited by the label.But these efforts also paved the road for the core of the automotive field, and have strong industry support to achieve all this.For example, under the sponsorship of SEMI, ASME and three IEEE associations, the new heterogeneous integrated roadmap (HIR) focuses on various micro -microelectronicDesign, materials and packaging problems to formulate roadmaps for the semiconductor industry.Their current focus includes 2.5D, 3D-IC, wafer-level packaging, integrated photonology, MEMS and sensors, and system-level packaging (SIP), aerospace, cars, etc.
At the recent 2023 heterogeneous integration Global Summit, representatives from AMD, application materials, Sun Moonlight, Panlin Group, MediaTek, Micron, Onto Innovation, TSMC, etc. all showed strong support for Chiclet.Another organization that supports Chiclet is Chiclet Design Exchange (CDX) working group. It is part of the open domain specific architecture (ODSA) and the Open Computing Project Foundation (OCP).Chiclet Design Exchange (CDX) Articles of Association focuses on the various characteristics of Chiclet and Chiclet, including 2.5D stacks and 3D  integrated circuit  (3D-IC) electrical, mechanical and thermal design exchange standards.Its representatives include ANSYS, Apply Materials, ARM, Ayar Labs, Broadcom, Cadence, Intel, Macom, Marvell, Microsemi, NXP, SIEMENS EDA, SYNOPSYS, etc.
Motor companies' requirements for each core grain function are still in a dramatic state, and Fritz of Siemens pointed out.One extreme has these problems, and the other has these problems.This is a sweet place.This is what you need.These are the types of companies that can carry out such work, and then you can combine them together.So this interoperability is nothing big.OEM may say that I must handle all the possibilities, which makes things too complicated.Another choice is that they may say, ‘this is like high -speed PCIe.If I want to communicate from one person to another, I already know what to do.I have the driver running my operating system.This will solve many problems, I believe this is the result.
A way of general core grain development?
Looking forward to the future, core grains will become the focus of the automotive and chip industry, which will involve everything from core grain IP to memory interconnection and customized options and restrictions.
For example, Ruisa Electronics announced its next -generation SoC and MCU in November 2023.The company aims at all the main applications in the automotive digital field, including information about its fifth-generation R-CAR SOC. The SOC is facing high-performance applications and adopts advanced packaging inner core grain integration technology to provide more than a larger car engineer with greater greater than car engineers.Customized flexibility they design.
Ruisa pointed out that if the driving assistance system (ADAS) requires higher artificial intelligence performance, engineers will be able to integrate artificial intelligence accelerators into a single chip.The company said that this route map was formulated after cooperation and discussion with OEM customers for many years. These customers have always called for a method that accelerates development without affecting quality, including designing and.Verification software.
As the demand for increasing on -demand computing continues to increase and the demand for higher levels of autonomy in the future, we have seen the challenges of the expansion of single -film solutions and meeting market performance in the next few years.Said with strategic director Vasanth Waran.Chiclet enables the calculation solution to expand and surpass market demand.He pointed out
Ruisa Electronics announced that it has started to create a core -based product series specifically for the automotive market.
　Standard interface allows SOC customization
At present, the standard processor (this is a place that uses most cores today) and how many overlap between the core grains developed for automobile applications.But as this technology is transferred to the new market, basic technology and development will definitely promote each other.
David Ridgeway, the product manager of the SynopSys IP acceleration solution team, said: Whether it is AI accelerator or ADAS car application, customers need standard interface IP blocks.It is important to provide a full -verified IP subsystem to support the subsystem components used in the customer SOC around the IP customization requirements.When I say customization, you may not realize how customized the custom IP that can be customized in the PHY end and controller side in the past 10 to 20 years.For example, PCI Express has grown from PCIe Gen 3 to Gen 4, then to Gen 5, and now it has developed to Gen 6.The controller can be configured to support the smaller link width, including 1 X16, 2 X8 or 4 X4.Our subsystem IP team cooperates with customers to ensure that all customized requirements are met.
For artificial intelligence applications, signals and power integrity are extremely important for meeting their performance.Almost all of our customers are seeking the limit of challenge to achieve the width rate of memory bandwidth as possible so that their TPU can handle more transactions per second.Whenever the application is cloud computing or artificial intelligence, customers want to get a fast response speed.

Entering phases will be difficult and need to be changed.In order to ensure interoperability, enough parts of the automotive ecosystem and supply chain must gather together, including hardware and software developers, foundries, OSAT, and materials and equipment suppliers.

Figure 1: Including processors, numbers, PHY, and verified IP modules can help developers realize the entire SOC
The final goal of optimizing the PPA is to improve efficiency, which makes it particularly attractive in automotive applications.When UCIE matures, the overall performance is expected to be improved.For example, Ucie can provide 28 to 224 GB/S/mm shoreline bandwidth in the standard packaging, and the coastline bandwidth of 165 to 1317 GB/S/mm can be provided in the package.This means that performance has increased by 20 to 100 times.Reduce delay from 20 nan seconds to 2 nano -seconds represent 10 times the improvement.Another advantage is that the power efficiency has increased by about 10 times, which are 0.5 PJ/B (standard packaging) and 0.25 PJ/B (packaging).The key is to shorten the interface distance as much as possible.
　In order to optimize the core grain design, the UCIE Alliance provides some suggestions:
Consider the architecture cutting line (ie, the core of the core), and optimize power consumption, delay, silicon area and IP reuse.For example, customizing a core grain that requires cutting -edge process nodes, and reusing other cores on the old node may affect costs and time;
It is necessary to target packaging hot seals, hotspots, core grain layouts, and I/O wiring and sectional planning heat and mechanical packaging constraints;
You need to carefully select the process node, especially in the context of the relevant power transmission scheme;
The test strategy of core grain and packaging/assembly is needed to pre -found to ensure that silicon problems are found during the core grain test stage, rather than assemble them after the packaging;